The present invention relates to a method of manufacturing a semiconductor device.
A dual damascene method that is a low-cost process of manufacture is used mainly when forming Cu wires on a device. The etch depth for wiring trench (film thickness of etching) directly relates to the cross-sectional area of Cu wires buried in subsequent processes and affects wiring resistance and/or capacitance. Accordingly, the etch uniformity and process stability of wiring trenches are especially important in a dual damascene method.
Japanese Patent Laid-Open No. 2003-332421 discloses a wire processing method using an etch stop layer. The problem of etch un-uniformity is solved by the use of an etch stop layer. However, this solution increases manufacturing costs since a process of forming the etch stop layer is added.
Japanese Patents Laid-Open Nos. 10-229122 and 2005-353698 disclose methods of etching insulating layers without using etch stop layers. In such methods of processing insulating layers as mentioned above, there arises a problem of etch un-uniformity originated from the instability of etching apparatus or from fluctuations in the ambient atmosphere within a chamber.
Japanese Patent Laid-Open No. 2004-71731 discloses an etching method not requiring the use of etch stop layers in a dual damascene method. In this method, a so-called low-k dielectric layer having relative permittivity lower than that of SiO2 and an SiO2 layer covering the dielectric layer (cap layer) are respectively etched under different conditions to form wiring trenches. Specifically, the SiO2 layer is etched under the condition with a higher selection ratio for the low-k dielectric layer, and then the low-k dielectric layer is etched under the condition with a lower selection ratio for the low-k dielectric layer.
However, the method disclosed in Japanese Patent Laid-Open No. 2004-71731 has not been able to solve the problem of etch un-uniformity. The inventor of the present application has newly discovered that the cause of this is that the thickness of a deposition layer formed in the bottom of each trench significantly varies within a wafer during the etching of a second insulating layer, if the etching of the second insulating layer is stopped at a point where a first insulating layer is exposed when successively etching a laminated layer composed of the first insulating layer and the second insulating layer formed thereon. This irregularity of thickness degrades the uniformity of processing shape resulting from the processing of the first insulating layer.